Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow

Colin J Ihrig author Alex K Jones author

Format:Paperback

Publisher:VDM Verlag

Published:30th Dec '08

Currently unavailable, and unfortunately no date known when it will be back

Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow cover

This paperback, "Improving Performance and Reducing Power with Hardware Acceleration - Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow" from Colin J Ihrig & Alex K Jones, was published 30th December 2008 by VDM Verlag.

ISBN: 9783639106909

Dimensions: 229mm x 152mm x 5mm

Weight: 141g

96 pages